1. Field of the Invention
The present invention relates, e.g., to memory devices and, in preferred embodiments, to a multi-valued memory device using carbon nanotube and nanowire FET.
2. Background Discussion
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art. Throughout this disclosure, the phrases carbon nanotube (CNT) and nanowire (NW) will be used interchangeably. For the purposes of this disclosure, both CNTs and NWs can be used interchangeably.
Traditionally a memory cell stores only 1 bit (binary) of information, i.e., either ‘0’ or ‘1’. However, if the memory cell is capable of storing more values besides ‘0’ or ‘1’ (known as a multi-valued memory cell), the overall memory size can be significantly reduced compared to a memory consisting of 1 bit cells for storing a similar amount of information. That is, traditionally the storage capacity of a memory cell has a direct relationship with the amount of area that memory cell occupies.
For example, using a 2 bit multi-valued cell, capable of storing any of 4 (22) values, the memory size can be reduced by two times compared to a memory consisting of 1 bit cells. Similarly, a three times reduction in size of the memory device can be achieved by using 3 bit cells; a four times reduction in size of the memory device can be achieved by using 4 bit cells and so on.
Previously, multi-valued ROM (read only memory) has been implemented through various different means. For example, a multivalued ROM has been implemented by engineering different threshold voltages of the cell transistor, representing different memory values through implantation. However, introducing various levels of implantation is a complex process and is not cost effective.
The problem has also attempted to be solved by varying the width of the transistor, however this solution has the disadvantage of providing unreliable operation. Also, varying the transistor size substantially contributes to a larger memory cell size, thereby severely limiting the advantages of the multi-valued ROM.
FIG. 1(a) shows a schematic diagram of a conventional field effect transistor (FET) with a channel consisting of CNTs/NWs. This is known as a carbon nanotube field effect transistor (CNFET). Conversely, a nanowire field effect transistor is known as an NWFET. The ON current of the transistor is determined by the characteristics and number of the CNTs/NWs. The ON current in these kinds of transistors vary linearly with the number of CNTs/NWs comprising the channel.
That is, the more CNTs/NWs are used as the transistor channel, the greater the ON current will be. A CNFET/NWFET works by applying a voltage to the gate of the electrode. This voltage induces an electric field which envelopes the CNTs/NWs. When the CNTs/NWs are in an electric field, their internal resistance decreases. This reduced internal resistance allows current to flow through the CNTs/NWs. The more CNTs/NWs are used as the transistor channel, the higher the ON current will be when a voltage is applied to the gate.